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課程資訊

課程名稱	數位系統設計 Digital System Design
開課學期	109-2
授課對象	電機資訊學院電機工程學系
授課教師	吳安宇
課號	EE4041
課程識別碼	901 43500
班次
學分	3.0
全/半年	半年
必/選修	選修
上課時間	星期四7,8,9(14:20~17:20)
上課地點	電二144
備註	總人數上限：40人
Ceiba 課程網頁	http://ceiba.ntu.edu.tw/1092_DSD
課程簡介影片
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課程概述	Digital System Design Introduction Fundamentals of Hardware Description Language Logic Design at Register Transfer Level Logic Design with Behavior Coding, Design Validation Synthesizable Coding of Verilog Coding Style and Verification Tool Synthesis Tool Usage Complexity Management and Performance Improvement Implementation Project: MIPS Processor
課程目標	Basics: Basic overview of digital systems Front-end cell-based design flow, theory & practice Refinement and improvement issues for digital systems Presentation: Implementation project Peer competetion for advanced design features Oral presentation
課程要求	Prerequisite: Switch circuits and logic designs Electronics Grading: Homework: 30% (HW1:5% HW2:5% HW3:10% HW4: 10%) Midterm Exam: 30% Machine Test: 5% Final Project: 30% Impression: 5% (Attendance/Attitude)
預期每週課後學習時數
Office Hours
指定閱讀	待補
參考書目	Slides in courses are the main materials Related textbooks can be referred to: “Verilog HDL: Digital design and modeling,” Joseph Cavanagh, CRC Press, 2007. “Computer organization and design: The hardware/software interface,” David A. Patterson and John L. Hennessy, 2014, 5th Edition. “Computer organization and design: The hardware/software interface,” David A. Patterson and John L. Hennessy, RISC-V Edition. “Digital system designs and practices: Using Verilog HDL and FPGAs," Ming-Bo Lin, Wiley, 2008.
評量方式 (僅供參考)

課程進度

週次	日期	單元主題
第1週	2/25	1. Course overview 2. Workstation tutorial
第2週	3/04	1. HDL v.s. IC technology (Prof. Wu) 2. HDL_Fundamentals (TA Frank Chuang)
第10週	4/29	Midterm Exam
第12週	5/13	On-line lectures for Pipeline MIPS
第13週	5/20	Online lectures for design guideline
第16週	6/10	Updated syllabus and schedule
第18週	6/24	1. Final report at 1pm @ 6/24 2. 報告繳交 Deadline：6/29